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Issue No.07 - July (1982 vol.31)
pp: 609-616
T.E. Mangir , Mangir Associates
ABSTRACT
In order to take full advantage of VLSI, new design methods are necessary to improve the yield and testability. Designs which incorporate redundancy to improve the yields of high density memory chips are well known. The goal of this paper is to motivate the extension of this technique to other types of VLSI logic circuits. The benefits and the limitations of on-chip modularization and the use of spare elements are presented, and significant yield improvements are shown to be possible.
INDEX TERMS
VLSI fault tolerance, Interconnect area estimates, redundancy partitioning, redundancy placement, regular designs, VLSI yield improvement
CITATION
T.E. Mangir, A. Avizienis, "Fault-Tolerant Design for VLSI: Effect of Interconnect Requirements on Yield Improvement of VLSI Designs", IEEE Transactions on Computers, vol.31, no. 7, pp. 609-616, July 1982, doi:10.1109/TC.1982.1676058
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