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Issue No.07 - July (1982 vol.31)
pp: 596-602
S. Kaneda , Musashino Electrical Communication Laboratory, Nippon Telegraph and Telephone Public Corporation
ABSTRACT
In a memory that uses byte-organized memory chips, each containing b (=2) output bits, a single chip failure is likely to affect many bits within a byte. Single byte error correcting?double byte error detecting codes (SbEC?DbED codes) are used in this kind of memory system to increase reliability.
INDEX TERMS
single byte error correcting? double byte error detecting codes, Byte-organized memory chips, error correcting codes, LSI implementation, reliability
CITATION
S. Kaneda, E. Fujiwara, "Single Byte Error Correcting?Double Byte Error Detecting Codes for Memory Systems", IEEE Transactions on Computers, vol.31, no. 7, pp. 596-602, July 1982, doi:10.1109/TC.1982.1676056
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