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J.H. Patel, Coordinated Science Laboratory, and the Department of Electrical Engineering, University of Illinois
A new method of concurrent error detection in the Arithmetic and Logic Units (ALU's) is proposed. This method, called "Recomputing with Shifted Operands" (RESO), can detect errors in both the arithmetic and logic operations. RESO uses the principle of time redundancy in detecting the errors and achieves its error detection capability through the use of the already existing replicated hardware in the form of identical bit slices. It is shown that for most practical ALU implementations, including the carry-lookahead adders, the RESO technique will detect all errors caused by faults in a bit-slice or a specific subcircuit of the bit slice. The fault model used is more general than the commonly assumed stuck-at fault model. Our fault model assumes that the faults are confined to a small area of the circuit and that the precise nature of the faults is not known. This model is very appropriate for the VLSI circuits.
Index Terms:
VLSI faults, ALU, bit-sliced ALU, concurrent error detection, fault detection, time redundancy, VLSI circuits
Citation:
J.H. Patel, L.Y. Fung, "Concurrent Error Detection in ALU's by Recomputing with Shifted Operands," IEEE Transactions on Computers, vol. 31, no. 7, pp. 589-595, July 1982, doi:10.1109/TC.1982.1676055
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