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June 1982 (vol. 31 no. 6)
pp. 540-546
F.J. Taylor, Department of Electrical and Computer Engineering, University of Cincinnati
Recently, residue arithmetic has received increased attention in the open literature. Using table lookup methods and high-speed memory, modular arithmetic has been demonstrated. However, the memory size limitation of ECL, bipolar, and high-speed MOS limits the admissible size of the moduli used in the numbering system. In this paper the moduli size limitation is overcome using VLSI technology, special architectures, and moduli choice. A residue multiplier having a 48?72 bit dynamic range, capable of performing 10M multiplication/s is reported.
Index Terms:
residue arithmetic, Modular arithmetic, multiplication
Citation:
F.J. Taylor, "A VLSI Residue Arithmetic Multiplier," IEEE Transactions on Computers, vol. 31, no. 6, pp. 540-546, June 1982, doi:10.1109/TC.1982.1676036
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