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MP/C: A Multiprocessor/Computer Architecture
May 1982 (vol. 31 no. 5)
pp. 455-473
B.W. Arden, Department of Electrical Engineering and Computer Science, Princeton University
A computer architecture for concurrent computing is proposed which has the shared memory aspect of tightly coupled multiprocessor systems and also the connection simplicity associated with message-connected, loosely-coupled multicomputer systems. A large address space is dynamically partitioned into contiguous segments that can be accessed by a single processor. The partitioning is accomplished by switching the system buses. The completion of a concurrent process is signaled by a processor's return to an idle state and the reattachment of its memory segment to the neighboring active processor. In effect, the assignment of an address sequence and the activation of a processor is a process-fork operation, and the processor deactivation and memory segment reattachment is a process-join. Following a description of the MP/C structure and operation, programming conventions are explained and demonstrated. Applications include tree-structured multiprocessing, recursive and nondeterministic procedures, very high precision numerical calculations, process-structured operating systems, and others. The linear MP/C structure is extensible to higher dimensions. A two-dimensional system is described and its application is discussed. Finally, performance issues are presented, and the MP/C architecture is compared with related designs.
Index Terms:
tree-structured computer, Computer architecture, multicomputers, multiprocessors, supersystems, switched bus
Citation:
B.W. Arden, R. Ginosar, "MP/C: A Multiprocessor/Computer Architecture," IEEE Transactions on Computers, vol. 31, no. 5, pp. 455-473, May 1982, doi:10.1109/TC.1982.1676022
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