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The Prime Memory System for Array Access
May 1982 (vol. 31 no. 5)
pp. 435-442
| ASCII Text | x | ||
| D.H. Lawrie, C.R. Vora, "The Prime Memory System for Array Access," IEEE Transactions on Computers, vol. 31, no. 5, pp. 435-442, May, 1982. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1982.1676020, author = {D.H. Lawrie and C.R. Vora}, title = {The Prime Memory System for Array Access}, journal ={IEEE Transactions on Computers}, volume = {31}, number = {5}, issn = {0018-9340}, year = {1982}, pages = {435-442}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1982.1676020}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - The Prime Memory System for Array Access IS - 5 SN - 0018-9340 SP435 EP442 EPD - 435-442 A1 - D.H. Lawrie, A1 - C.R. Vora, PY - 1982 KW - SIMD computer memory KW - Array access KW - Burroughs Scientific Processor (BSP) conflict-free array memory KW - memory system KW - parallel computer system VL - 31 JA - IEEE Transactions on Computers ER - | |||
In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.
Index Terms:
SIMD computer memory, Array access, Burroughs Scientific Processor (BSP) conflict-free array memory, memory system, parallel computer system
Citation:
D.H. Lawrie, C.R. Vora, "The Prime Memory System for Array Access," IEEE Transactions on Computers, vol. 31, no. 5, pp. 435-442, May 1982, doi:10.1109/TC.1982.1676020
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