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The Prime Memory System for Array Access
May 1982 (vol. 31 no. 5)
pp. 435-442
D.H. Lawrie, Department of Computer Science, University of Illinois
In this paper we describe a memory system designed for parallel array access. The system is based on the use of a prime nwnber of memories and a powerful combination of indexing hardware and data alignment switches. Particular emphasis is placed on the indexing equations and their implementation.
Index Terms:
SIMD computer memory, Array access, Burroughs Scientific Processor (BSP) conflict-free array memory, memory system, parallel computer system
Citation:
D.H. Lawrie, C.R. Vora, "The Prime Memory System for Array Access," IEEE Transactions on Computers, vol. 31, no. 5, pp. 435-442, May 1982, doi:10.1109/TC.1982.1676020
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