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H.J. Sips, Department of Applied Physics, Delft University of Technology
For the realization of a bit-sequential multiplier with operands of length n, Chen and Willoner1 suggest a circuitry consisting of 2n identical modules. It is shown that if a slightly different arrangement of the modules is taken, the number of modules is reduced to n. Furthermore, the implementation in circuit form can be made more simple.
Index Terms:
real-time algorithms, Computer arithmetic, on-line algorithms, parallel multiplier, pipe-lining
Citation:
H.J. Sips, "Comments on "An O(n) Parallel Multiplier with Bit-Sequential Input and Output"," IEEE Transactions on Computers, vol. 31, no. 4, pp. 325-327, April 1982, doi:10.1109/TC.1982.1676000
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