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A Regular Layout for Parallel Adders
March 1982 (vol. 31 no. 3)
pp. 260-264
R.P. Brent, Department of Computer Science, Australian National University
With VLSI architecture, the chip area and design regularity represent a better measure of cost than the conventional gate count. We show that addition of n-bit binary numbers can be performed on a chip with a regular layout in time proportional to log n and with area proportional to n.
Index Terms:
VLSI, Addition, area-time complexity, carry lookahead, circuit design, combinational logic, models of computation, parallel addition, parallel polynomial evaluation, prefix computation
Citation:
R.P. Brent, H.T. Kung, "A Regular Layout for Parallel Adders," IEEE Transactions on Computers, vol. 31, no. 3, pp. 260-264, March 1982, doi:10.1109/TC.1982.1675982
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