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Architecture for VLSI Design of Reed-Solomon Encoders
February 1982 (vol. 31 no. 2)
pp. 170-175
K.Y. Liu, Jet Propulsion Laboratory, California Institute of Technology
In this correspondence the logic structure of a universal VLSI chip called the symbol-slice Reed-Solomon (RS) encoder chip is presented. An RS encoder can be constructed by cascading and properly interconnecting a group of such VLSI chips. As a design example, it is shown that a (255, 223) RS encoder requiring around 40 discrete CMOS IC's may be replaced by an RS encoder consisting of four identical interconnected VLSI RS encoder chips. Besides the size advantage, the VLSI RS encoder also has the potential advantages of requiring less power and having a higher reliability.
Index Terms:
VLSI architecture, Data communication, data storage, error-correcting codes, Reed-Solomon encoders, space communications
Citation:
K.Y. Liu, "Architecture for VLSI Design of Reed-Solomon Encoders," IEEE Transactions on Computers, vol. 31, no. 2, pp. 170-175, Feb. 1982, doi:10.1109/TC.1982.1675964
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