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Fault Diagnosis of MOS Combinational Networks
February 1982 (vol. 31 no. 2)
pp. 129-139
Y.M. El-Ziq, Honeywell Corporate Computer Science Center
The increasing difficulties in testing large logic networks have generated the need for designing logic networks for testability. Computer algorithms for designing diagnosable metal oxide semiconductor (MOS) networks with and without fan-in, fan-out constraints were described in previous papers by the authors. In this two-part series, we discuss the testing of these designed networks.
Index Terms:
test generation, Automatic testing, computer-aided testing, computer algorithms, design for testability, diagnosable networks, fault detection, fault diagnosis, fault isolation, fault location, fault testing, MOS (metal oxide semiconductor), statistical results
Citation:
Y.M. El-Ziq, S.Y.H. Su, "Fault Diagnosis of MOS Combinational Networks," IEEE Transactions on Computers, vol. 31, no. 2, pp. 129-139, Feb. 1982, doi:10.1109/TC.1982.1675958
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