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Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications
February 1982 (vol. 31 no. 2)
pp. 110-118
| ASCII Text | x | ||
| D.D. Riley, R.J. Baron, "Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications," IEEE Transactions on Computers, vol. 31, no. 2, pp. 110-118, February, 1982. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1982.1675956, author = {D.D. Riley and R.J. Baron}, title = {Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications}, journal ={IEEE Transactions on Computers}, volume = {31}, number = {2}, issn = {0018-9340}, year = {1982}, pages = {110-118}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1982.1675956}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications IS - 2 SN - 0018-9340 SP110 EP118 EPD - 110-118 A1 - D.D. Riley, A1 - R.J. Baron, PY - 1982 KW - synchronous transmission KW - Interprocessor communications KW - message oriented network KW - multiprocessor simulation VL - 31 JA - IEEE Transactions on Computers ER - | |||
A message oriented interprocessor communication network is proposed that utilizes a simple fixed algorithm to store-and-forward short messages over directed data lines. The modular design of the network permits message transmission along a variable number of processors. Simulations of the network's performance indicate that for appropriate message loads the network transmits messages in time proportional to the square root of the number of processors served.
Index Terms:
synchronous transmission, Interprocessor communications, message oriented network, multiprocessor simulation
Citation:
D.D. Riley, R.J. Baron, "Design and Evaluation of a Synchronous Triangular Interconnection Scheme for Interprocessor Communications," IEEE Transactions on Computers, vol. 31, no. 2, pp. 110-118, Feb. 1982, doi:10.1109/TC.1982.1675956
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