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Automated Synthesis of Digital Hardware
February 1982 (vol. 31 no. 2)
pp. 93-109
L.J. Hafer, Department of Computing Science, Simon Fraser University
This paper describes a portion of the Carnegie-Mellon University Design Automation (CMU-DA) research. This part involves the design and construction of a data-memory allocator, consisting of a set of algorithms and data structures which synthesize hardware at the register-transfer level from a behavioral description written in ISP. The allocator selects registers and data operators and interconnects them with data paths to form a data part capable of implementing the data operations specified in the behavior. Results indicate that the allocator's performance compares favorably with a human designer when designing an elevator controller and a reduced PDP-8/E. Although optimal designs cannot be guaranteed, upper bounds for the number of components used can be derived from the ISP description.
Index Terms:
register-transfer level, Automated synthesis, computer-aided design, design automation, hardware-descriptive language, hardware specification, ISP, logic design
Citation:
L.J. Hafer, A.C. Parker, "Automated Synthesis of Digital Hardware," IEEE Transactions on Computers, vol. 31, no. 2, pp. 93-109, Feb. 1982, doi:10.1109/TC.1982.1675955
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