CSDL - IEEE Transactions on Computers

IEEE Computer Society (PDF)

pp. c2

Introduction (PDF)

pp. 821-822

A Design of Programmable Logic Arrays with Universal Tests (Abstract)

H. Fujiwara, Department of Electronic Engineering, Osaka University

K. Kinoshita

pp. 823-828

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A Hardware Approach to Self-Testing of Large Programmable Logic Arrays (PDF)

W. Daehin, Lehrstuhl f?r Theoretische Elektrotechnik, University of Hannover

J. Mucha

pp. 829-833

A Testable Design of Iterative Logic Arrays (Abstract)

R. Parthasarathy, Department of Electrical and Computer Engineering, University of Iowa

S.M. Reddy

pp. 833-841

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Design of Easily Testable Bit-Sliced Systems (PDF)

T. Sridhar, Texas Instruments, Inc.

J.P. Hayes

pp. 842-854

Multiple Fault Testing of Large Circuits by Single Fault Test Sets (Abstract)

V.K. Agarwal, Department of Electrical Engineering, McGill University

A.S.F. Fung

pp. 855-865

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Design for Autonomous Test (PDF)

E.J. McCluskey, Center for Reliable Computing, Computer Systems Laboratory, Departments of Computer Science and Electrical Engineering, Stanford University

S. Bozorgui-Nesbat

pp. 866-875

Design of Testable Structures Defined by Simple Loops (Abstract)

J.A. Abraham, Coordinated Science Laboratory, University of Illinois

D.D. Gajski

pp. 875-884

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