Issue No.11 - November (1981 vol.30)
T. Sridhar , Texas Instruments, Inc.
Bit-sliced systems are formed by interconnecting identical slices or cells to form a one-dimensional iterative logic array (ILA). This paper presents several design techniques for constructing easily testable bit-sliced systems. Properties of ILA's that simplify their testing are examined. C-testable ILA's, which require a constant number of test patterns independent of the array size, are characterized, and a method for making an arbitrary ILA C-testable is presented. A new testability concept for arrays called I-testability is introduced. I-testability ensures that identical test responses can be obtained from every cell in an ILA, and thus simplifies response verification. I-testable ILA's are characterized, as well as CI-testable arrays, which are simultaneously C- and I-testable. A method of making an arbitrary ILA CI-testable is presented. The application of C- and I-testing to the design of bit-sliced (micro-) computers is investigated. For this purpose a family of easily testable processor slices is described. The design of a self-testing CPU based on I-testing is discussed, and compared with a more conventional self-testing design.
test generation, Bit-sliced systems, design for testability, fault modeling, iterative logic arrays, self-testing
T. Sridhar, J.P. Hayes, "Design of Easily Testable Bit-Sliced Systems", IEEE Transactions on Computers, vol.30, no. 11, pp. 842-854, November 1981, doi:10.1109/TC.1981.1675715