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October 1981 (vol. 30 no. 10)
pp. 813-818
C.V. Ramamoorthy, Department of Electrical Engineering and Computer Science, University of California
In this correspondence we have presented a technique to find the degradation in memory and buffer utilization due to dependencies of accesses issued by a pipelined computer. When a dependency occurs, the request stream to the memory is interrupted and the utilization of the memory decreases. The dependency is then resolved in the pipelined computer. New requests are generated and the utilization gradually builds up to a maximum. The delay between the time a dependency occurs and the time the dependency is resolved depends highly on the method used in the pipelined computer to resolve the dependency. Hence, the evaluations of a specific computer is too restrictive in scope. A general organization of a pipelined computer is proposed. We evaluate the degradation in memory utilization due to dependencies using a Markovian model. This is validated against a detailed simulation model. The analysis is based on the memory configuration (Organization I) and simulation results with no dependencies that are presented in a separate paper in this issue.
Index Terms:
pipelined computer, Access dependencies, buffer utilization, interleaved memories, Markovian model, memory utilization
Citation:
C.V. Ramamoorthy, B.W. Wah, "The Degradation in Memory Utilization Due to Dependencies," IEEE Transactions on Computers, vol. 30, no. 10, pp. 813-818, Oct. 1981, doi:10.1109/TC.1981.1675702
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