This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility
July 1981 (vol. 30 no. 7)
pp. 513-519
The microprogrammed filter engine (MICE) is a fast, microprogrammable processor built with ECL bit slices (Motorola ECL 10800 series) intended primarily to be used as an on-line data filtering engine for high energy physics experiments. In this note we describe the use of a hardware description language used to model and simulate the hardware during its development. We treat the problem of describing a pipelined, horizontal (112 bits wide) host machine, implemented using bit slices with considerable potential for parallelism. Several levels of modeling are conceptually applicable to a problem of this nature and the note describes the thorough process followed before we decided on a particular style of description and simulation.
Index Terms:
simulation and modeling, Bit slices, hardware description languages, microprogramming
Citation:
A. Van Dam, M. Barbacci, C. Halatsis, J. Joosten, M. Letheren, "Simulation of a Horizontal Bit-Sliced Processor Using the ISPS Architecture Simulation Facility," IEEE Transactions on Computers, vol. 30, no. 7, pp. 513-519, July 1981, doi:10.1109/TC.1981.1675830
Usage of this product signifies your acceptance of the Terms of Use.