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| ASCII Text | x | ||
| S.H. Unger, "Double-Edge-Triggered Flip-Flops," IEEE Transactions on Computers, vol. 30, no. 6, pp. 447-451, June, 1981. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1981.1675811, author = {S.H. Unger}, title = {Double-Edge-Triggered Flip-Flops}, journal ={IEEE Transactions on Computers}, volume = {30}, number = {6}, issn = {0018-9340}, year = {1981}, pages = {447-451}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1981.1675811}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Double-Edge-Triggered Flip-Flops IS - 6 SN - 0018-9340 SP447 EP451 EPD - 447-451 A1 - S.H. Unger, PY - 1981 KW - sequential circuits KW - Asynchronous KW - clock pulses KW - decomposition KW - D-flip-flop KW - edge triggering KW - flip-flops KW - JK-flip-flops KW - sequential circuits KW - Asynchronous KW - clock pulses KW - decomposition KW - D-flip-flop KW - edge triggering KW - flip-flops KW - JK-flip-flops VL - 30 JA - IEEE Transactions on Computers ER - | |||
A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FF's behave in a complementary manner. Thus, these FF's can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FF's, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.
Index Terms:
sequential circuits,Asynchronous,clock pulses,decomposition,D-flip-flop,edge triggering,flip-flops,JK-flip-flops,sequential circuits,Asynchronous,clock pulses,decomposition,D-flip-flop,edge triggering,flip-flops,JK-flip-flops
Citation:
S.H. Unger, "Double-Edge-Triggered Flip-Flops," IEEE Transactions on Computers, vol. 30, no. 6, pp. 447-451, June 1981, doi:10.1109/TC.1981.1675811
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