Issue No.06 - June (1981 vol.30)
S.H. Unger , Department of Computer Science, Columbia University
A conventional positive-edge-triggered flip-flop (FF) senses and responds to the control input or inputs at the time the clock input is changing from 0 to 1. It does not respond at all to changes in the opposite direction. Negative-edge-triggered FF's behave in a complementary manner. Thus, these FF's can respond at most once per clock pulse cycle. It is proposed that double-edge-triggered (DET) FF's, responding to both edges of the clock pulse would have advantages with respect to speed and energy dissipation.
sequential circuits, Asynchronous, clock pulses, decomposition, D-flip-flop, edge triggering, flip-flops, JK-flip-flops, sequential circuits, Asynchronous, clock pulses, decomposition, D-flip-flop, edge triggering, flip-flops, JK-flip-flops
S.H. Unger, "Double-Edge-Triggered Flip-Flops", IEEE Transactions on Computers, vol.30, no. 6, pp. 447-451, June 1981, doi:10.1109/TC.1981.1675811