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A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks
May 1981 (vol. 30 no. 5)
pp. 356-358
null Se June Hong, IBM T. J. Watson Research Center
A simple procedure to produce a minimum length test set for a parity network is presented. If M is the largest fan in of any EX-OR gate element in the tree, 2M test patterns are chosen by considering only 2M test sequences, of length 2M, assigned to each signal line.
Index Terms:
parity tree, EX-OR gate, optimum testing
Citation:
null Se June Hong, D.L. Ostapko, "A Simple Procedure to Generate Optimum Test Patterns for Parity Logic Networks," IEEE Transactions on Computers, vol. 30, no. 5, pp. 356-358, May 1981, doi:10.1109/TC.1981.1675793
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