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Optimal Layout of CMOS Functional Arrays
May 1981 (vol. 30 no. 5)
pp. 305-312
T. Uehara, Computer Science Laboratory, Fujitsu Laboratories
Designers of MOS LSI circuits can take advantage of complex functional cells in order to achieve better performance. This paper discusses the implementation of a random logic function on an array of CMOS transistors. A graph-theoretical algorithm which minimizes the size of an array is presented. This method is useful for the design of cells used in conventional design automation systems.
Index Terms:
LSI layout, CMOS circuit design, CMOS functional arrays, computer-aided design, design automation, LSI design automation
Citation:
T. Uehara, W.M. Vancleemput, "Optimal Layout of CMOS Functional Arrays," IEEE Transactions on Computers, vol. 30, no. 5, pp. 305-312, May 1981, doi:10.1109/TC.1981.1675787
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