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Issue No.03 - March (1981 vol.30)
pp: 237-240
A. Sengupta , Computer Science Unit, Indian Statistical Institute
ABSTRACT
This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.
INDEX TERMS
linear code, Correction, fault detection, fault masking, fault-tolerant machine
CITATION
A. Sengupta, D.K. Chattopadhyay, A. Palit, A.K. Bandyopadhyay, A.K. Choudhury, "Realization of Fault-Tolerant Machines?Linear Code Application", IEEE Transactions on Computers, vol.30, no. 3, pp. 237-240, March 1981, doi:10.1109/TC.1981.1675762
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