This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
Realization of Fault-Tolerant Machines?Linear Code Application
March 1981 (vol. 30 no. 3)
pp. 237-240
A. Sengupta, Computer Science Unit, Indian Statistical Institute
This correspondence deals with the fault-tolerant realization of a sequential machine using error-correcting (n,k) linear codes. Earlier works in the same area confine their attention to modified Reed-Muller Code and perfect Hamming Code and achieve the realization using a number of majority logic gates, which makes the entire realization quite complex. The realization discussed in this paper needs a smaller number of circuit components with less complexity.
Index Terms:
linear code, Correction, fault detection, fault masking, fault-tolerant machine
Citation:
A. Sengupta, D.K. Chattopadhyay, A. Palit, A.K. Bandyopadhyay, A.K. Choudhury, "Realization of Fault-Tolerant Machines?Linear Code Application," IEEE Transactions on Computers, vol. 30, no. 3, pp. 237-240, March 1981, doi:10.1109/TC.1981.1675762
Usage of this product signifies your acceptance of the Terms of Use.