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An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits
March 1981 (vol. 30 no. 3)
pp. 215-222
| ASCII Text | x | ||
| P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, vol. 30, no. 3, pp. 215-222, March, 1981. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1981.1675757, author = {P. Goel}, title = {An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits}, journal ={IEEE Transactions on Computers}, volume = {30}, number = {3}, issn = {0018-9340}, year = {1981}, pages = {215-222}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1981.1675757}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits IS - 3 SN - 0018-9340 SP215 EP222 EPD - 215-222 A1 - P. Goel, PY - 1981 KW - untestable fault KW - Combinational logic KW - D-algorithm KW - decision tree KW - error correction KW - implicit enumeration KW - stuck faults KW - test generation VL - 30 JA - IEEE Transactions on Computers ER - | |||
The D-algorithm (DALG) is shown to be ineffective for the class of combinational logic circuits that is used to implement error correction and translation (ECAT) functions. PODEM (path-oriented decision making) is a new test generation algorithm for combinational logic circuits. PODEM uses an implicit enumeration approach analogous to that used for solving 0-1 integer programming problems. It is shown that PODEM is very efficient for ECAT circuits and is significantly more efficient than DALG over the general spectrum of combinational logic circuits. A distinctive feature of PODEM is its simplicity when compared to the D-algorithm. PODEM is a complete algorithm in that it will generate a test if one exists. Heuristics are used to achieve an efficient implicit search of the space of all possible primary input patterns until either a test is found or the space is exhausted.
Index Terms:
untestable fault, Combinational logic, D-algorithm, decision tree, error correction, implicit enumeration, stuck faults, test generation
Citation:
P. Goel, "An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits," IEEE Transactions on Computers, vol. 30, no. 3, pp. 215-222, March 1981, doi:10.1109/TC.1981.1675757
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