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Ternary Rate-Multipliers
October 1980 (vol. 29 no. 10)
pp. 929-931
H.T. Mouftah, Department of Electrical Engineering, Queen's University
This correspondence describes an application of COS/MOS integrated circuits in the design of ternary rate-multipliers. The logical implementation of two types of ternary rate-multiplier is described. The first type produces an unevenly spaced output pulse train, while in the second one the output pulses are uniformly spaced. Advantages and disadvantages of the two types are presented.
Index Terms:
three-valued logic, Integrated circuits, rate-multipliers
Citation:
H.T. Mouftah, K.C. Smith, Z.G. Vranesic, "Ternary Rate-Multipliers," IEEE Transactions on Computers, vol. 29, no. 10, pp. 929-931, Oct. 1980, doi:10.1109/TC.1980.1675477
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