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Ternary Rate-Multipliers
October 1980 (vol. 29 no. 10)
pp. 929-931
ASCII Text
x 
 
H.T. Mouftah, K.C. Smith, Z.G. Vranesic, "Ternary Rate-Multipliers," IEEE Transactions on Computers, vol. 29, no. 10, pp. 929-931, October, 1980.
 
 
BibTex
x
 
@article{ 10.1109/TC.1980.1675477,
author = {H.T. Mouftah and K.C. Smith and Z.G. Vranesic},
title = {Ternary Rate-Multipliers},
journal ={IEEE Transactions on Computers},
volume = {29},
number = {10},
issn = {0018-9340},
year = {1980},
pages = {929-931},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1980.1675477},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - Ternary Rate-Multipliers
IS - 10
SN - 0018-9340
SP929
EP931
EPD - 929-931
A1 - H.T. Mouftah,
A1 - K.C. Smith,
A1 - Z.G. Vranesic,
PY - 1980
KW - three-valued logic
KW - Integrated circuits
KW - rate-multipliers
VL - 29
JA - IEEE Transactions on Computers
ER -
 
H.T. Mouftah, Department of Electrical Engineering, Queen's University
This correspondence describes an application of COS/MOS integrated circuits in the design of ternary rate-multipliers. The logical implementation of two types of ternary rate-multiplier is described. The first type produces an unevenly spaced output pulse train, while in the second one the output pulses are uniformly spaced. Advantages and disadvantages of the two types are presented.
Index Terms:
three-valued logic, Integrated circuits, rate-multipliers
Citation:
H.T. Mouftah, K.C. Smith, Z.G. Vranesic, "Ternary Rate-Multipliers," IEEE Transactions on Computers, vol. 29, no. 10, pp. 929-931, Oct. 1980, doi:10.1109/TC.1980.1675477
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