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Efficient Function Implementation for Bit-Serial Parallel Processors
September 1980 (vol. 29 no. 9)
pp. 841-844
A.P. Reeves, School of Electrical Engineering, Purdue University
Parallel processors with bit-serial processing elements (PE's) usually implement arithmetic functions by a sequence of word-level arithmetic operations; however, basic operations must be specified at the bit level. In this correspondence the possibility of more efficiently implementing a function with a special tailored sequence of bit-serial operations is considered. A general scheme is described for generating efficient programs to implement arbitrary functions on bit-serial-arithmetic processors. This scheme is based on logic design methodology and involves designing a logic network to realize a desired function. The parallel processor is then used to efficiently simulate a set of these networks. Heuristic design algorithms are used to generate the logic networks; several algorithms are described and compared with some benchmark functions. Several efficient PE designs are described and analyzed.
Index Terms:
universal logic modules, Binary array processing, bit-serial arithmetic, logic design algorithms, parallel processing, Reed-Muller canonic form, two-input gate networks
A.P. Reeves, J.D. Bruner, "Efficient Function Implementation for Bit-Serial Parallel Processors," IEEE Transactions on Computers, vol. 29, no. 9, pp. 841-844, Sept. 1980, doi:10.1109/TC.1980.1675685
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