|
| This Article | ||
| ||
| Share | ||
| Bibliographic References | ||
| Add to: | ||
| | ||
| Search | ||
| ||
| ASCII Text | x | ||
| K.E. Batcher, "Design of a Massively Parallel Processor," IEEE Transactions on Computers, vol. 29, no. 9, pp. 836-840, September, 1980. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1980.1675684, author = {K.E. Batcher}, title = {Design of a Massively Parallel Processor}, journal ={IEEE Transactions on Computers}, volume = {29}, number = {9}, issn = {0018-9340}, year = {1980}, pages = {836-840}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1980.1675684}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Design of a Massively Parallel Processor IS - 9 SN - 0018-9340 SP836 EP840 EPD - 836-840 A1 - K.E. Batcher, PY - 1980 KW - satellite imagery KW - Array processing KW - bit-slice processing KW - computer architecture KW - image processing KW - parallel processing VL - 29 JA - IEEE Transactions on Computers ER - | |||
The massively parallel processor (MPP) system is designed to process satellite imagery at high rates. A large number (16 384) of processing elements (PE's) are configured in a square array. For optimum performance on operands of arbitrary length, processing is performed in a bit-serial manner. On 8-bit integer data, addition can occur at 6553 million operations per second (MOPS) and multiplication at 1861 MOPS. On 32-bit floating-point data, addition can occur at 430 MOPS and multiplication at 216 MOPS.
Index Terms:
satellite imagery, Array processing, bit-slice processing, computer architecture, image processing, parallel processing
Citation:
K.E. Batcher, "Design of a Massively Parallel Processor," IEEE Transactions on Computers, vol. 29, no. 9, pp. 836-840, Sept. 1980, doi:10.1109/TC.1980.1675684
Usage of this product signifies your acceptance of the Terms of Use.

