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Issue No.08 - August (1980 vol.29)
pp: 753-756
N.M. Martin , Applied Research Laboratories, University of Texas
ABSTRACT
A high-speed parallel adder of digitally represented numbers called the conditional-sum early completion adder (CSCA) will be described. The CSCA design is based on the computation of "conditional" sums, carries, and column completion detection logic.
INDEX TERMS
high speed adder, Addition, compute arithmetic, conditional-sum adder, CSA, end-around carry
CITATION
N.M. Martin, S.P. Hufnagel, "Conditional-Sum Early Completion Adder Logic", IEEE Transactions on Computers, vol.29, no. 8, pp. 753-756, August 1980, doi:10.1109/TC.1980.1675663
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