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Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability
June 1980 (vol. 29 no. 6)
pp. 527-531
J. Galiay, Soci?t? pour l'Etude et la Fabrication de Circuits Int?gr?s Sp?ciaux (EFCIS)
At the end of an IC production line, integrated circuits are generally submitted to three kinds of tests: 1) parametric tests to check electrical characteristics (voltage, current, power consumption), 2) dynamic tests to check response times under nominal operating conditions, and 3) functional tests to check its logical behavior.
Index Terms:
test sequences generation, Failure characterization, fault models, testability improvement, testing procedures
Citation:
J. Galiay, Y. Crouzet, M. Vergniault, "Physical Versus Logical Fault Models MOS LSI Circuits: Impact on Their Testability," IEEE Transactions on Computers, vol. 29, no. 6, pp. 527-531, June 1980, doi:10.1109/TC.1980.1675614
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