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Syndrome-Testable Design of Combinational Circuits
June 1980 (vol. 29 no. 6)
pp. 442-451
J. Savir, IBM Thomas J. Watson Research Center
Classical testing of combinational circuits requires a list of the fault-free response of the circuit to the test set. For most practical circuits implemented today the large storage requirement for such a list makes such a test procedure very expensive. Moreover, the computational cost to generate the test set increases exponentially with the circuit size.
Index Terms:
stuck-at fault, Combinational circuit, fan-out-free circuit, minterm, prime implicant, single fault
Citation:
J. Savir, "Syndrome-Testable Design of Combinational Circuits," IEEE Transactions on Computers, vol. 29, no. 6, pp. 442-451, June 1980, doi:10.1109/TC.1980.1675603
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