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Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection
May 1980 (vol. 29 no. 5)
pp. 410-416
| ASCII Text | x | ||
| J. Savir, "Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection," IEEE Transactions on Computers, vol. 29, no. 5, pp. 410-416, May, 1980. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1980.1675595, author = {J. Savir}, title = {Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection}, journal ={IEEE Transactions on Computers}, volume = {29}, number = {5}, issn = {0018-9340}, year = {1980}, pages = {410-416}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1980.1675595}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection IS - 5 SN - 0018-9340 SP410 EP416 EPD - 410-416 A1 - J. Savir, PY - 1980 KW - random testing KW - Error latency KW - intermittent fault detection KW - irredundant circuit KW - maximum likelihood estimator VL - 29 JA - IEEE Transactions on Computers ER - | |||
Intermittent faults in combinational circuits may appear and disappear randomly; hence, their detection requires many repeated applications of test vectors. Since testing reduces the time available for computation, it is necessary to efficiently minimize the time required for a test, while still achieving a high degree of fault detection.
Index Terms:
random testing, Error latency, intermittent fault detection, irredundant circuit, maximum likelihood estimator
Citation:
J. Savir, "Testing for Single Intermittent Failures in Combinational Circuits by Maximizing the Probability of Fault Detection," IEEE Transactions on Computers, vol. 29, no. 5, pp. 410-416, May 1980, doi:10.1109/TC.1980.1675595
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