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May 1980 (vol. 29 no. 5)
pp. 393-398
D.D. Gajski, Department of Computer Science, University of Illinois
A subclass of generalized parallel counters, called parallel compressors, is introduced in this correspondence. Under present-day packaging technology, parallel compressors with their higher compression ratio and fewer input/output pins are more efficient in multiple operand addition and multiplication than parallel counters. Cost and time bounds are obtained for schemes using parallel compressors for reduction of N summands to m summands. Furthermore, a method for synthesizing large parallel counters using only one type of parallel compressor is given.
Index Terms:
parallel counters, Associative processors, carry-shower counters, content- addressable memory, elementary logic functions, fast multipliers, high-speed arithmetic, multiple-operand addition
Citation:
D.D. Gajski, "Parallel Compressors," IEEE Transactions on Computers, vol. 29, no. 5, pp. 393-398, May 1980, doi:10.1109/TC.1980.1675589
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