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A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures
March 1980 (vol. 29 no. 3)
pp. 254-258
S.Y.H. Su, Department of Computer Science, School of Advanced Technology, State University of New York
This paper deals with a method for designing a digital system which will remain operational in spite of the failure of some of its components. A scheme and its realization are presented for automatically reconfiguring a 5MR (five modular redundancy system or 5-input majority voting system) into a triple modular redundancy (TMR) system under a single or double module failures. The scheme can tolerate a double fault followed by a single fault which can neither be tolerated by a 5MR nor by a hybrid redundancy system with a TMR core. It uses no spare units and the circuit realization is relatively simple. The modular structure of the logic design for the proposed scheme should make the testing of the system easier. The scheme can be used in both binary and multivalued systems.
Index Terms:
system design, Fault-tolerant computing, fault-tolerant design, fault-tolerant systems, hybrid redundancy, multiple failures, multiple-valued logic, N-modular redundancy, redundancy scheme, self- repair systems
S.Y.H. Su, E. DuCasse, "A Hardware Redundancy Reconfiguration Scheme for Tolerating Multiple Module Failures," IEEE Transactions on Computers, vol. 29, no. 3, pp. 254-258, March 1980, doi:10.1109/TC.1980.1675557
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