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An Experimental Delay Test Generator for LSI Logic
March 1980 (vol. 29 no. 3)
pp. 235-248
J.D. Lesser, IBM Thomas J. Watson Research Center
Delay testing is a test procedure to verify the timing performance of manufactured logic networks. When a level-sensitive scan design (LSSD) discipline is used, all networks are combinational. Appropriate test patterns are selected on the basis of certain theoretical criteria. These criteria are embodied in an experimental test generation program. The program has successfully produced sets of delay tests for large logic networks. The average coverage achieved by these tests faDs within 95.8 percent to 99.9 percent of optimal.
Index Terms:
test generation, Delay testing
Citation:
J.D. Lesser, J.J. Shedletsky, "An Experimental Delay Test Generator for LSI Logic," IEEE Transactions on Computers, vol. 29, no. 3, pp. 235-248, March 1980, doi:10.1109/TC.1980.1675555
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