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A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic
February 1980 (vol. 29 no. 2)
pp. 134-144
J. Zeman, Institute of Telecommunications, Swiss Federal Institute of Technology
This paper describes a general-purpose digital-signal processor which is constructed with 4 bit bipolar microprocessor slices. The signal processor is microprogrammable and contains special features which allow it to employ distributed arithmetic. Hence, the processor can achieve high sampling rates without using a hardware multiplier unit. The processor's architecture is presented and its micro-order structure is examined. The processor wordlength is 16 bit; its basic cycle time, 300 ns; its data memory size, 2K words; its control store size, 256 ? 56 bits. It consumes 48 W of power and has special address processing hardware. Experimental results with a twelfth-order digital filter are demonstrated. The signal processor is also compared with several other signal processors of its class described in the literature.
J. Zeman, H.T., Jr. Nagle, "A High-Speed Microprogrammable Digital Signal Processor Employing Distributed Arithmetic," IEEE Transactions on Computers, vol. 29, no. 2, pp. 134-144, Feb. 1980, doi:10.1109/TC.1980.1675537
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