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An 0(n) Parallel Multiplier with BitSequential Input and Output
October 1979 (vol. 28 no. 10)
pp. 721727
ASCII Text  x  
null INgo Chen, R. Willoner, "An 0(n) Parallel Multiplier with BitSequential Input and Output," IEEE Transactions on Computers, vol. 28, no. 10, pp. 721727, October, 1979.  
BibTex  x  
@article{ 10.1109/TC.1979.1675239, author = {null INgo Chen and R. Willoner}, title = {An 0(n) Parallel Multiplier with BitSequential Input and Output}, journal ={IEEE Transactions on Computers}, volume = {28}, number = {10}, issn = {00189340}, year = {1979}, pages = {721727}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1979.1675239}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  An 0(n) Parallel Multiplier with BitSequential Input and Output IS  10 SN  00189340 SP721 EP727 EPD  721727 A1  null INgo Chen, A1  R. Willoner, PY  1979 KW  realtime algorithms KW  Computer arithmetic KW  online algorithms KW  parallel multiplier KW  pipelining VL  28 JA  IEEE Transactions on Computers ER   
Previous proposals for fast multipliers are discussed, along with a summary of the known theoretical limitations of such designs. Then, a new parallel multiplier with a very simple configuration is suggested. This multiplier operates in time 0(n), where n is the maximum of the lengths of the multiplier and multiplicand, both of which are fixed point, expressed in binary notation. It is a logical circuit consisting of 2n modules, each being only slightly more complex than a full adder; instead of three inputs and two outputs, each module has five inputs and three outputs. A logical circuit realization is given for the modules. But perhaps the most significant aspect of this design is the property that the input is required only bitsequentially and the output is generated bitsequentially, both at the rate of one bit per time step, least significant bit first. The advantages of such bitsequential input and output arithmetic units are described.
Index Terms:
realtime algorithms, Computer arithmetic, online algorithms, parallel multiplier, pipelining
Citation:
null INgo Chen, R. Willoner, "An 0(n) Parallel Multiplier with BitSequential Input and Output," IEEE Transactions on Computers, vol. 28, no. 10, pp. 721727, Oct. 1979, doi:10.1109/TC.1979.1675239
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