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Issue No.09 - September (1979 vol.28)
pp: 648-659
null Hung Chi Lai , Microtechnology Corp.
ABSTRACT
Parallel binary adders of n bits long in single-rail input logic which have a minimum number of NOR gates are derived in this paper. The minimality of the number of NOR gates is proved for an arbitrary value of n. Also, it is proved that the adders must be a cascade of basic modules and that there exist many different types of basic modules. These adders have fewer gates and shorter net gate delays (or fewer connections) than the widely used carry-ripple adders which are a cascade of one-bit full adders. Design procedures of such adders are described, based on the integer-programming logic design method. There are many solutions but adders with few connections and those with few net gate delays (all these adders have the minimum number of gates) are shown as important examples. Altbough these adders are designed with NOR gates, the results in this paper are applicable to adders with NAND gates by duality conversion.
INDEX TERMS
NOR gates, Adders, carry-ripple adders, logic design, minimum adders, NAND gates
CITATION
null Hung Chi Lai, S. Muroga, "Minimum Parallel Binary Adders with NOR (NAND) Gates", IEEE Transactions on Computers, vol.28, no. 9, pp. 648-659, September 1979, doi:10.1109/TC.1979.1675433
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