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Iterative Realization of Multivalued Logic Systems
April 1979 (vol. 28 no. 4)
pp. 306-310
V.P. Srini, Department of Computer Science, University of Southwestern Louisiana
The realization of multivalued combinational functions and sequential machines by using arrays of one type of cells is considered. The algebra used for the multivalued logic system has two binary operations and a set of unary operations. Each of these operations is realized by a cellular array. The cells are combinational and implemented by using binary logic gates. The cells are also designed so that all unrestricted multiple faults in arrays of these cells are detectable. Multivalued combinational functions, storage elements, and sequential machines are realized by interconnecting the arrays realizing the operations.
Index Terms:
multivalued logic., Cell, cellular array, fault detection, + gate, gate, U gates, general fault, multiple faults
Citation:
V.P. Srini, "Iterative Realization of Multivalued Logic Systems," IEEE Transactions on Computers, vol. 28, no. 4, pp. 306-310, April 1979, doi:10.1109/TC.1979.1675351
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