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Implementing Parallel Counters with FourValued Threshold Logic
March 1979 (vol. 28 no. 3)
pp. 200204
ASCII Text  x  
K.W. Current, D.A. Mow, "Implementing Parallel Counters with FourValued Threshold Logic," IEEE Transactions on Computers, vol. 28, no. 3, pp. 200204, March, 1979.  
BibTex  x  
@article{ 10.1109/TC.1979.1675320, author = {K.W. Current and D.A. Mow}, title = {Implementing Parallel Counters with FourValued Threshold Logic}, journal ={IEEE Transactions on Computers}, volume = {28}, number = {3}, issn = {00189340}, year = {1979}, pages = {200204}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1979.1675320}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, }  
RefWorks Procite/RefMan/Endnote  x  
TY  JOUR JO  IEEE Transactions on Computers TI  Implementing Parallel Counters with FourValued Threshold Logic IS  3 SN  00189340 SP200 EP204 EPD  200204 A1  K.W. Current, A1  D.A. Mow, PY  1979 KW  threshold logic KW  Fourvalved logic full adders KW  multivalued logic KW  parallel counters VL  28 JA  IEEE Transactions on Computers ER   
Parallel counters are multipleinput circuits that count the number of their inputs that are in a given state. They are useful in implementing parallel multipliers, digital summers, digital correlators, and in other digital signal processing capacities. In this paper, the implementation of parallel counters with fourvalued threshold logic is described and these implementations are compared to their binary full adder network counter equivalents. This logic form was selected because of the increasing importance of implementing stateoftheart digital signal processing systems in largescaleintegrated (LSI) circuit form. LSI circuit designs are, in general, limited by the number of metal signal and power lines that must be placed upon the chip's surface, not by the number of active and passive devices used. Since each signal variable in fourvalued logic may assume four logic states, twice the information carrying capacity as in binary logic, an over 50percent savings in the total number of signal variables required to implement the parallel counter results. Also, with the circuits we describe here, approximately 50 percent fewer transistors and resistors are necessary for the implementation of fourvalued logic parallel counters. These savings are attainable with a modest tradeoff in speed and power.
Index Terms:
threshold logic, Fourvalved logic full adders, multivalued logic, parallel counters
Citation:
K.W. Current, D.A. Mow, "Implementing Parallel Counters with FourValued Threshold Logic," IEEE Transactions on Computers, vol. 28, no. 3, pp. 200204, March 1979, doi:10.1109/TC.1979.1675320
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