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| ASCII Text | x | ||
| N. Gaitanis, C. Halatsis, "A New Double-Rank Realization of Sequential Machines," IEEE Transactions on Computers, vol. 27, no. 12, pp. 1137-1143, December, 1978. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1978.1675016, author = {N. Gaitanis and C. Halatsis}, title = {A New Double-Rank Realization of Sequential Machines}, journal ={IEEE Transactions on Computers}, volume = {27}, number = {12}, issn = {0018-9340}, year = {1978}, pages = {1137-1143}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1978.1675016}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - A New Double-Rank Realization of Sequential Machines IS - 12 SN - 0018-9340 SP1137 EP1143 EPD - 1137-1143 A1 - N. Gaitanis, A1 - C. Halatsis, PY - 1978 KW - state assignment KW - Boolean memory KW - cyclic Boolean memory KW - double-rank circuits KW - excitation function KW - excitation matrix KW - flip-flop memory KW - n-flop KW - sequential machines VL - 27 JA - IEEE Transactions on Computers ER - | |||
A new type of double-rank sequential circuit is presented in this paper. This new type, called Type 4, differs from its predecessor types in that it employs a Boolean memory as rank-1 memory instead of flip-flops. The Boolean memory used is an aggregate of symmetric Boolean memories with 1-out-of-n state encodings. A procedure for realizing a sequential machine by a Type 4 double-rank sequential circuit is also presented in the paper.
Index Terms:
state assignment, Boolean memory, cyclic Boolean memory, double-rank circuits, excitation function, excitation matrix, flip-flop memory, n-flop, sequential machines
Citation:
N. Gaitanis, C. Halatsis, "A New Double-Rank Realization of Sequential Machines," IEEE Transactions on Computers, vol. 27, no. 12, pp. 1137-1143, Dec. 1978, doi:10.1109/TC.1978.1675016
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