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An Algorithm for Optimal NAND Cascade Logic Synthesis
December 1978 (vol. 27 no. 12)
pp. 1099-1111
C.A. Papachristou, Department of Electrical Engineering, Drexel University
This paper is concerned with optimal synthesis of switching logic by a limited depth tree-like network, the NAND cascade. This cascade consists of a number of complete three-level, fan-in restricted NAND trees feeding a NAND collector. The goal of the proposed synthesis is to minimize the number of NAND trees of the cascade, which in turn will minimize its overall depth, i.e., the delay time of the cascade.
Index Terms:
switching functions, Combinational logic, NAND gates, NAND trees, NAND cascade, NAND tree formula, NAND collector
Citation:
C.A. Papachristou, "An Algorithm for Optimal NAND Cascade Logic Synthesis," IEEE Transactions on Computers, vol. 27, no. 12, pp. 1099-1111, Dec. 1978, doi:10.1109/TC.1978.1675012
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