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Efficient Algorithms for Testing Semiconductor Random-Access Memories
June 1978 (vol. 27 no. 6)
pp. 572-576
R. Nair, Coordinated Science Laboratory, University of Illinois
A fault model which views faults in semiconductor random-access memories at a functional level instead of at a basic gate level is presented. An efficient 0(n) algorithm to detect all faults in the fault model is described. The fault model is then extended to incorporate more complex faults. An 0(n ? log2 n) algorithm is presented for one such extended fault model.
Index Terms:
test complexity, Coupling, fault models, memories, testing algorithm
Citation:
R. Nair, S.M. Thatte, J.A. Abraham, "Efficient Algorithms for Testing Semiconductor Random-Access Memories," IEEE Transactions on Computers, vol. 27, no. 6, pp. 572-576, June 1978, doi:10.1109/TC.1978.1675150
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