This Article 
   
 Share 
   
 Bibliographic References 
   
 Add to: 
 
Digg
Furl
Spurl
Blink
Simpy
Google
Del.icio.us
Y!MyWeb
 
 Search 
   
A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems
May 1978 (vol. 27 no. 5)
pp. 455-459
S.M. Reddy, Division of Information Engineering, University of Iowa
To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.
Index Terms:
memories, Binary codes, byte-error detecting codes, byte-per-card systems, linear codes
Citation:
S.M. Reddy, "A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems," IEEE Transactions on Computers, vol. 27, no. 5, pp. 455-459, May 1978, doi:10.1109/TC.1978.1675126
Usage of this product signifies your acceptance of the Terms of Use.