Issue No.05 - May (1978 vol.27)
S.M. Reddy , Division of Information Engineering, University of Iowa
To improve the reliability of computer memories error-correcting and/or error-detecting codes have been successfully used. To provide for error control in systems organized to have b bits per card a new class of codes for simultaneous error correction and error detection is given.
memories, Binary codes, byte-error detecting codes, byte-per-card systems, linear codes
S.M. Reddy, "A Class of Linear Codes for Error Control in Byte-per-Card Organized Digital Systems", IEEE Transactions on Computers, vol.27, no. 5, pp. 455-459, May 1978, doi:10.1109/TC.1978.1675126