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Memory Hierarchy Configuration Analysis
May 1978 (vol. 27 no. 5)
pp. 408-413
T.A. Welch, Sperry Research Center
This paper presents an analytical study of speed-cost tradeoffs in memory hierarchy design. It develops an optimization criterion by which average access time, i. e., memory system delay, is minimized under a cost constraint for a hierarchy with given memory sizes and access probabilities. Using a power function assumption relating speed and cost of memory units, it is shown that an optimized hierarchy has the property of balanced cost and delay distributions, in that each memory unit makes the same percentage contribution to memory system cost as it makes to average system access delay. Using the same assumption, a lower bound on average access time is developed, showing that access time is roughly related to a cube-root averaging of access probabilities. These results provide useful tools for developing memory hierarchy design strategies and for evaluating data placement algorithms.
Index Terms:
speed-cost tradeoffs, Access time minimization, memory access probabilities, memory hierarchy analysis, memory performance bounds, memory systems
Citation:
T.A. Welch, "Memory Hierarchy Configuration Analysis," IEEE Transactions on Computers, vol. 27, no. 5, pp. 408-413, May 1978, doi:10.1109/TC.1978.1675120
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