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Minimizing Latency in CCD Memories
March 1978 (vol. 27 no. 3)
pp. 252-254
S.H. Fuller, Department of Computer Science, Carnegie-Mellon University
Serial memories built from charge-coupled devices (CCD's) offer an opportunity for minimizing latency times not available with the more conventional drum and disk (serial) memory units. Let r be the ratio of the maximum to the minimum clocking rates for the CCD memory. We show that in many practical situations the average latency can be reduced from 1/2 to 1/(1 + vr) of a revolution time if the optimal clocking strategy is used when the CCD is idle.
Index Terms:
serial memories, Charge-coupled devices, disks, rotational latency
Citation:
S.H. Fuller, P.F. McGehearty, "Minimizing Latency in CCD Memories," IEEE Transactions on Computers, vol. 27, no. 3, pp. 252-254, March 1978, doi:10.1109/TC.1978.1675079
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