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9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
March 1978 (vol. 27 no. 3)
pp. 193-200
ASCII Text
x 
 
C.W. Cha, W.E. Donath, F. Ozguner, "9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits," IEEE Transactions on Computers, vol. 27, no. 3, pp. 193-200, March, 1978.
 
 
BibTex
x
 
@article{ 10.1109/TC.1978.1675071,
author = {C.W. Cha and W.E. Donath and F. Ozguner},
title = {9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits},
journal ={IEEE Transactions on Computers},
volume = {27},
number = {3},
issn = {0018-9340},
year = {1978},
pages = {193-200},
doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1978.1675071},
publisher = {IEEE Computer Society},
address = {Los Alamitos, CA, USA},
}
 
 
RefWorks Procite/RefMan/Endnote
x 
 
TY - JOUR
JO - IEEE Transactions on Computers
TI - 9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits
IS - 3
SN - 0018-9340
SP193
EP200
EPD - 193-200
A1 - C.W. Cha,
A1 - W.E. Donath,
A1 - F. Ozguner,
PY - 1978
KW - testing
KW - Backward implication
KW - fault
KW - forward forcing
KW - multiple paths
KW - sensitized path
VL - 27
JA - IEEE Transactions on Computers
ER -
 
C.W. Cha, IBM SPD East Fishkill
An algorithm for generating test patterns for combinational circuits has been developed and programmed. The algorithm is definitive and finds a test for all faults including those that require multiple paths to be sensitized, by sensitizing a single path at a time and trying at most each single path. This is achieved by using a new calculus based on nine values (0,1,D,D?,0/D,0/D?, 1/D,1/D?,U). One path is deliberately sensitized while the alternative paths are assigned values which permit the option of desensitizing or sensitizing them as the sensitized path is developed. Experimental results are presented for a variety of cases.
Index Terms:
testing, Backward implication, fault, forward forcing, multiple paths, sensitized path
Citation:
C.W. Cha, W.E. Donath, F. Ozguner, "9-V Algorithm for Test Pattern Generation of Combinational Digital Circuits," IEEE Transactions on Computers, vol. 27, no. 3, pp. 193-200, March 1978, doi:10.1109/TC.1978.1675071
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