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Issue No.01 - January (1978 vol.27)
pp: 36-41
J.P. Hayes , Department of Electrical Engineering and the Department of Computer Science, University of Southern California
ABSTRACT
The problem of generating minimum-length transition count (TC) tests is examined for combinational logic circuits whose behavior can be defined by an n-row fault table. Methods are presented for generating TC tests of length n+2 and 2n-1 for fault detection and fault location, respectively. It is shown that these tests are optimal with respect to the class of n-row fault tables in the sense that there exist n-row fault tables that cannot be covered by shorter TC tests. The practical significance of these tests is discussed.
INDEX TERMS
transition counting, Combinational circuits, fault detection, fault location, fault tables, optimal tests, test generation
CITATION
J.P. Hayes, "Generation of Optimal Transition Count Tests", IEEE Transactions on Computers, vol.27, no. 1, pp. 36-41, January 1978, doi:10.1109/TC.1978.1674950
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