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November 1977 (vol. 26 no. 11)
pp. 1144-1147
A novel technique for address generation is presented in this correspondence. This scheme has two useful features. Addresses are generated with check bits as an integral part of the address in order to provide multi-fault-detection capability. To date, there exists no such scheme with this feature. Secondly, the addresses generated through this scheme are pseudorandom; therefore, they can be used for storage hierarchies using hash coding techniques.
Index Terms:
Address generator, binary counter, error-correcting codes, fault-tolerant computing, linear-feedback shift register.
Citation:
M.Y. Hsiao, A.M. Patel, D.K. Pradhan, "Store Address Generator with On-Line Fault-Detection Capability," IEEE Transactions on Computers, vol. 26, no. 11, pp. 1144-1147, Nov. 1977, doi:10.1109/TC.1977.1674762
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