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An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories
November 1977 (vol. 26 no. 11)
pp. 1141-1144
| ASCII Text | x | ||
| J., Jr. Knaizuk, C.R.P. Hartmann, "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories," IEEE Transactions on Computers, vol. 26, no. 11, pp. 1141-1144, November, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674761, author = {J., Jr. Knaizuk and C.R.P. Hartmann}, title = {An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {11}, issn = {0018-9340}, year = {1977}, pages = {1141-1144}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674761}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories IS - 11 SN - 0018-9340 SP1141 EP1144 EPD - 1141-1144 A1 - J., Jr. Knaizuk, A1 - C.R.P. Hartmann, PY - 1977 KW - Fault detection stuck-at aults KW - optimal algorithm KW - random access memories. VL - 26 JA - IEEE Transactions on Computers ER - | |||
This correspondence presents an optimal algorithm to detect any single "stuck-at-i," "stuck-at-O" fault and any combination of "stuck-at-I," "stuck-at-O" multiple faults in a random access memory using only the n-bit memory address register input and m-bit memory buffer register input and output lines. It is shown that this algorithm requires 4 X 2n memory accesses.
Index Terms:
Fault detection stuck-at aults, optimal algorithm, random access memories.
Citation:
J., Jr. Knaizuk, C.R.P. Hartmann, "An Optimal Algorithm for Testing Stuck-at Faults in Random Access Memories," IEEE Transactions on Computers, vol. 26, no. 11, pp. 1141-1144, Nov. 1977, doi:10.1109/TC.1977.1674761
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