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An Incremental Computer
November 1977 (vol. 26 no. 11)
pp. 1072-1081
H. Brafmen, Stanford Linear Accelerator, Stanford University
The article describes a variable high-speed incremental computer that adopts the basic concept underlying a digital differential analyzer (DDA). Its structure closely resembles that of a microprocessor and includes the following features: floating-point arithmetic, a word-length transfer with the elimination of a residue (R) register, multibit multiplication, and a flexible software scheme of interconnections that includes the use of a stack to avoid redundant operations. The proposed structure has been simulated by solving a variety of differential equations with distinctly accurate results.
Index Terms:
Common random-access memory for the microprocessor (COMEM), digital differential analyzer (DDA), Operation Code and microinstruction mnemonics, simulation to various high-order differential equations, variable high-speed Incremental Computer (IC).
Citation:
H. Brafmen, B.J. Reuter, "An Incremental Computer," IEEE Transactions on Computers, vol. 26, no. 11, pp. 1072-1081, Nov. 1977, doi:10.1109/TC.1977.1674753
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