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Modular Design of Asynchronous Circuits Defined by Graphs
August 1977 (vol. 26 no. 8)
pp. 727-737
| ASCII Text | x | ||
| R. David, "Modular Design of Asynchronous Circuits Defined by Graphs," IEEE Transactions on Computers, vol. 26, no. 8, pp. 727-737, August, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674910, author = {R. David}, title = {Modular Design of Asynchronous Circuits Defined by Graphs}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {8}, issn = {0018-9340}, year = {1977}, pages = {727-737}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674910}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Modular Design of Asynchronous Circuits Defined by Graphs IS - 8 SN - 0018-9340 SP727 EP737 EPD - 727-737 A1 - R. David, PY - 1977 KW - Asynchronous circuits KW - description by graphs KW - modular networks KW - synthesis from graphs KW - synthesis without assignment KW - universal cell CUSA. VL - 26 JA - IEEE Transactions on Computers ER - | |||
An universal cell (CUSA) permits one to realize any asynchronous automaton by associating such a cell with a state and a connection with a transition. There is no internal variable assignment and all kinds of hazards are avoided. In the first part of the paper we shall present the principle of the CUSA and the synthesis method using flow tables. It is an original method which enables one to reduce the number of cells and useful connections. In the second part, the method is adapted to a synthesis from a flow graph. In this graph, a node is associated with a state, not necessarily a total state, and a branch with a connection. This synthesis method is easy and systematic. CUSA are now being produced by industry and are available as IC's.
Index Terms:
Asynchronous circuits, description by graphs, modular networks, synthesis from graphs, synthesis without assignment, universal cell CUSA.
Citation:
R. David, "Modular Design of Asynchronous Circuits Defined by Graphs," IEEE Transactions on Computers, vol. 26, no. 8, pp. 727-737, Aug. 1977, doi:10.1109/TC.1977.1674910
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