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Some Performance Issues in Multiprocessor System Design
May 1977 (vol. 26 no. 5)
pp. 506-511
| ASCII Text | x | ||
| D.P. Bhandarkar, "Some Performance Issues in Multiprocessor System Design," IEEE Transactions on Computers, vol. 26, no. 5, pp. 506-511, May, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674868, author = {D.P. Bhandarkar}, title = {Some Performance Issues in Multiprocessor System Design}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {5}, issn = {0018-9340}, year = {1977}, pages = {506-511}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674868}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - Some Performance Issues in Multiprocessor System Design IS - 5 SN - 0018-9340 SP506 EP511 EPD - 506-511 A1 - D.P. Bhandarkar, PY - 1977 KW - Memory interference KW - memory interleaving KW - multiprocessors KW - performance. VL - 26 JA - IEEE Transactions on Computers ER - | |||
Analytic and simulation models of memory interference have been reported in the literature. These models provide tools for analyzing various system architecture alternatives. Some of the design parameters are processor speed, memory speed, number of processors, number of memories, use of cache memories, high-order versus low-order interleaving, and memory allocation. This correspondence applies existing analytic and simulation models to the multiprocessor design space and presents guidelines for the multiprocessor system architect. Preferred design alternatives and tradeoffs are outlined.
Index Terms:
Memory interference, memory interleaving, multiprocessors, performance.
Citation:
D.P. Bhandarkar, "Some Performance Issues in Multiprocessor System Design," IEEE Transactions on Computers, vol. 26, no. 5, pp. 506-511, May 1977, doi:10.1109/TC.1977.1674868
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