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| ASCII Text | x | ||
| D.Y. Chang, D.J. Kuck, D.H. Lawrie, "On the Effective Bandwidth of Parallel Memories," IEEE Transactions on Computers, vol. 26, no. 5, pp. 480-490, May, 1977. | |||
| BibTex | x | ||
| @article{ 10.1109/TC.1977.1674865, author = {D.Y. Chang and D.J. Kuck and D.H. Lawrie}, title = {On the Effective Bandwidth of Parallel Memories}, journal ={IEEE Transactions on Computers}, volume = {26}, number = {5}, issn = {0018-9340}, year = {1977}, pages = {480-490}, doi = {http://doi.ieeecomputersociety.org/10.1109/TC.1977.1674865}, publisher = {IEEE Computer Society}, address = {Los Alamitos, CA, USA}, } | |||
| RefWorks Procite/RefMan/Endnote | x | ||
| TY - JOUR JO - IEEE Transactions on Computers TI - On the Effective Bandwidth of Parallel Memories IS - 5 SN - 0018-9340 SP480 EP490 EPD - 480-490 A1 - D.Y. Chang, A1 - D.J. Kuck, A1 - D.H. Lawrie, PY - 1977 KW - Array memory system KW - parallel memory bandwidth KW - parallel memory performance KW - memory interference KW - multiprocessor performance. VL - 26 JA - IEEE Transactions on Computers ER - | |||
The object of this paper is to bring together several models of interleaved or parallel memory systems and to expose some of the underlying assumptions about the address streams in each model. We derive the performance for each model, either analytically or by simulation, and discuss why it yields better or worse performance than other models (e.g., because of dependencies in the address stream or hardware queues, etc.). We also show that the performance of a properly designed system can be a linear rather than a square root function of the number of memories and processors.
Index Terms:
Array memory system, parallel memory bandwidth, parallel memory performance, memory interference, multiprocessor performance.
Citation:
D.Y. Chang, D.J. Kuck, D.H. Lawrie, "On the Effective Bandwidth of Parallel Memories," IEEE Transactions on Computers, vol. 26, no. 5, pp. 480-490, May 1977, doi:10.1109/TC.1977.1674865
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